A flip-chip semiconductor package is a type of semiconductor package with its electrical connection being established by means of flip-chip technology. For example, in a flip-chip semiconductor package, an active surface of at least one semiconductor chip is attached to and electrically connected to a substrate via a plurality of solder bumps. Recently, such design has become a dominating packaging technique, because such design not only can reduce package size and decrease the ratio of the semiconductor chip to the substrate, it can also reduce impedance and enhance electrical functions as it does not require the use of bonding wires.
Referring to FIGS. 1A and 1B, a prior-art flip-chip semiconductor package is disclosed. First, a flip chip 10 is mounted on and electrically connected to a substrate 11 via a plurality of solder bumps 13, and then an underfill 12 is filled between the flip chip 10 and the substrate 11 so as to encapsulate and protect the solder bumps 13, and support the weight of the flip-chip 10. Similar techniques may be found in U.S. Pat. Nos. 6,225,704, 6,074,895, 6,372,544 and 5,218,234.
Nevertheless, owing to the surface tension of the underfill 12, after filling the underfill 12, only a minimum amount of coherence protection is provided for the corners of the flip chip 10. Moreover, due to a mismatch of coefficient of thermal expansion (CTE) between the flip chip 10 and the substrate 11, thermal stress and thermal deformation raised during the heat cycle of the semiconductor chip packaging is directly proportional to the corner-to-center distance, which can be expressed as δ(deformation)=α(coefficient of thermal expansion)*L(distance, when deformation =0)*Δt(change of temperature). In other words, as corners of the flip-chip 10 are the farthest from the center of the chip, the corners are subjected to the thermal stress and thermal deformation to the greatest extent. Furthermore, if the underfill 12 fails to provide sufficient protection, peripheral portions of the underfill 12 may be delaminated from the chip 10 (as indicated by S in FIG. 1B), thus undermining the underfill 12. Moreover, if such peripheral delamination is turned into a more severe situation, the delamination may be expanded from the peripheral to the center of the underfill 12, thereby affecting the electrical functions of the solder bumps 13 badly.
Moreover, as the mainstream products of semiconductor chips are manufactured by ever-advancing process technology from 90 nm node to 65 nm node, 45 nm node, or even 32 nm node, it is necessary to introduce a dielectric material with a low dielectric constant K in order to overcome resistor-capacitor (RC) time delay due to ever-dwindling line widths of semiconductor chips. This thereby allows metal traces within a chip to be arranged in position close to each other, so as to prevent signal leakage and interference as well as increasing transmission speed. However, the low-K dielectric material typically has a hard and brittle characteristic and therefore is susceptible to delamination, because the low-K dielectric material cannot efficiently absorb and eliminate thermal stress generated during fabrication processes.
Referring to FIG. 2, U.S. Pat. No. 6,734,567 suggests a flip-chip semiconductor package comprising a flip chip 20 and a substrate 21, wherein the substrate 21 has a metal ring 24 formed thereon so as to prevent underfill delamination extending from the periphery to the center of the substrate 21. Nevertheless, U.S. Pat. No. 6,734,567 does not disclose or teach a way to prevent delamination between the underfill and the flip chip 20 and delamination inside the flip chip 20.
In view of the foregoing drawbacks, industrial manufacturers use underfills of low Young's modulus to absorb thermal stress in order to solve the thermal stress problem arising from different coefficients of thermal expansion (CTE). However, simply applying an underfill with low Young's modulus cannot provide a strong and sufficient supporting strength for the solder bumps. On the other hand, an underfill with high Young's modulus may provide a greater supporting strength for the solder bumps, but the underfill with high Young's modulus makes the flip chip subject to thermal stress and therefore results in delamination. Accordingly, a lot of researches and studies have to be done in order to find underfills suitable for connecting chips and substrates of different sizes and kinds, however these researches and studies are often laborious, cost-consuming, time-consuming and test-based, thereby leading to a prolonged fabrication process and higher fabrication costs.
Hence, a need still remains for providing a solution that can effectively prevent delamination between the underfill and the chip, delamination between the underfill and the substrate, and delamination within the chip, as well as protecting the solder bumps.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.